In electronic data processing systems, a particularly useful form of semiconductor integrated logic circuit has been the domino CMOS logic circuit. It has been described in some detail in the literature, for example, in a paper authored by R. H. Krambeck, et al., entitled "High-Speed Compact Circuits with CMOS," published in IEEE Journal of Solid-State Circuits, Vol. SC-17, pp. 614-619 (1982). Briefly, such a circuit comprises a collection of logic gates at least some of which deliver logic signals as logic input signals to others, the entire circuit being periodically activated by a single clock edge during each period, so that each gate computes its prescribed logic function during an evaluation phase that occurs once per clock period. That is, whenever that single clock edge occurs, the gates all enter an evaluation phase during which each gate computes the correspondingly prescribed function, one gate after another, somewhat analogously to the falling down of one domino after another in a network of dominoes.
More specifically, in a domino CMOS circuit each logic gate includes an array of NMOS pull-down driver transistors that are connected for receiving the gate's logic input signals and that are interconnected for implementing the prescribed logic function to be computed by such gate. Each gate further includes a clocked PMOS pull-up transistor for implementing a precharging of an output node of the gate during a precharge phase of each clock period, the clocked NMOS transistor acting as a power switch for suppressing discharge of the output node during the precharge phase. The clocked PMOS pull-up transistor, the output node, the array of NMOS driver transistors, and the NMOS power switch are serially connected between a high voltage level power line (V.sub.DD) and a low voltage level power line (V.sub.SS), typically ground. The output node is connected to the input terminal of a static (unclocked) inverter, and the output terminal of this inverter serves as the output terminal of the gate, i.e., where a voltage corresponding to the prescribed logic function (high vs. low, 1 vs. 0) is developed during the evaluation phase of each period immediately following the precharge phase thereof.
During each precharge phase of the clock, the output node of each gate is precharged high by the on state of the clocked PMOS pull-up transistor which the path from the output node to the low level is kept open by the off state of the clocked NMOS power switch. The precharge phase ends and the evaluation phase begins when the power switch is turned on while the clocked PMOS pull-up transistor is turned off, so that the output node can then discharge (or not) to ground through at least one closed path from the output node to the low level through the array of driver transistors (depending upon the logic values of the logic input signals thereto). A significant feature of the domino CMOS circuit is that it includes a plurality of logic gates, typically as many as 700, each gate implementing a prescribed logic function--with each transition from precharge to evaluation phase being induced by means of a single clock edge (or its complement) applied simultaneously to all clocked transistors in all logic gates of the circuit. Typically, a given domino CMOS gate (except for the first in a sequence of gates) receives as input signals some output signals from other gates in the same circuit, as well as perhaps from other sources.
To prevent spurious temporary input signals during the evaluation phase--i.e., signals which would prematurely discharge (pull-down) the output node, with no hope of subsequent restoration by pull-up during that same evaluation phase--it is important in domino CMOS to assure that in every gate no logic input signal should go from high to low during any evaluation phase--to avoid spurious discharge of the output node. To this end, the static inverter is inserted as a buffer between the output node of each domino gate and the drivers in any succeeding domino gate, i.e., any gate that receives signals from such output node. During any precharge--i.e., when the output node of every gate is momentarily at the high level due to pull-up by the clocked PMOS transistor--the corresponding buffer output at the output terminal of every such domino gate will therefore be low, so that any (NMOS) driver that receives as input the output of a (thus buffered) domino gate will receive a low level input and hence will always be off during the precharge phase. Thus, during each evaluation phase immediately following such precharge, the only transition (if any) that a domino gate output can make during an evaluation phase is from low to high, and never from high to low--the latter of which would spuriously pull-down (discharge) the output node to the low voltage level with no hope of restoration back to the high level during that same evaluation phase as would be desired in response to the input of low voltage level. In other words, a temporary initial (false) low level input which then goes high during an evaluation phase is the only allowed transition during evaluation. (Of course, an input signal which is supposed to be low during evaluation need not make any transition if it is already at the appropriate low voltage level during precharge.) As a result, there cannot be any spurious signals or "glitches" in the circuit.
Thus, all domino logic gates in a given circuit can be and are switched from precharge to evaluation phase--i.e., all pull-up transistors are switched from on to off--by means of same signal clock edge. Moreover, if all drivers in a given domino gate are supplied with properly timed logic signal inputs--that is, all inputs guaranteed to be low during all precharge phases--then the power switch for that gate can be omitted. Note that the output developed at the (buffered) output terminal of any domino gate is automatically a properly timed signal in this sense.
A domino CMOS logic circuit has a desirably small power consumption, since there is never a closed d.c. path from the high (V.sub.DD) to the low (V.sub.SS) level power line, and the use of a single clock edge to activate the entire domino circuit provides simple operation and full utilization of the speed of each logic gate.
A serious limitation on the use of domino CMOS in prior art arises from the above-mentioned requirement that the only transitions (if any) that any outputs from a domino CMOS gate that are used as inputs to another domino CMOS gate should experience during any evaluation phase are low to high transitions exclusively. However, in order to implement certain logic functions of two or more logic variables, A,B, . . . --such as EXCLUSIVE OR, XOR(A,B)=AB+AB, or EXCLUSIVE NOR, XNOR(A,B)=AB +AB--both a given logic signal A and its inverse A are required as logic signal inputs simultaneously to the same gate. But in domino CMOS all logic input signals must be low at the end of the precharge phase, as discussed above. Therefore, since a given logic signal and its inverse cannot both be low simultaneously, a domino CMOS gate requires special measures for implementing any of those logic functions--like XOR and XNOR(=AB+AB)--which contain any logic variable together with its inverse as input logic variables: if during an evaluation A goes from low to high, then in ordinary logic A would have to go from high to low-which is undesirable in domino CMOS. Consequently, logic circuits that are designed to implement such functions have required such special measures as the use of multiple clock edges--a scheme which undesirably complicates the logic circuitry and also suffers from slower operation (due to lost time), or have been designed in the forms of static CMOS gates, which are slower than domino CMOS gates. The resulting slower speed of operation is especially a serious problem in cases of many stages of cascaded gates, as in the case of parity trees, for example.